The present invention relates to encoding data for transmission through a channel and for decoding such encoded data after its transmission through a channel. In particular, the present invention relates to encoders and decoders in communication systems for information storage and retrieval.
Information that is transmitted from a source to a destination can be considered generically to pass through a channel. In some communication systems, the channel comprises electromagnetic radiation passing through the atmosphere. In other communication systems, the channel comprises a long conductor between the source and destination. Still other communication systems comprise a magnetic disk, where information from the source is stored on the disk and later retrieved from the disk for delivery to the destination.
In early storage systems, an analog read signal was generated from the disk and converted into digital data by assuming that a current digital value was unaffected by its predecessor values in the read signal. Later systems recognized that the writing and reading operations could be modeled as a communication channel and that this communication channel exhibited certain partial response characteristics in which neighboring values in the channel affected each other.
Using this channel model, many current systems utilize a Partial Response Maximum Likelihood (PRML) approach when attempting to detect and decode data read from a storage medium. Under PRML, a read signal is generated from the medium and sampled to produce a sequence of samples. These samples are then passed through a filter to fit the samples to a desired channel response. A detector then determines the most likely data sequence given the sequence of samples.
Typically, storage systems have channel responses of the form (1xe2x88x92D)(1+D)n, where D represents a delay of one time period and n is the order of the target that approximates the channel response. When n=2, the channel response is known as EPR4 and when n=3, the channel response is known as E2PR4 (also written as EEPR4). Expanding the basic equation above for each value of n produces target polynomials for each channel response of:
HEPR4(D)=1+Dxe2x88x92D2xe2x88x92D3xe2x80x83xe2x80x83EQ. 1
and
HEEPR4(D)=1+2Dxe2x88x922D3xe2x88x92D4xe2x80x83xe2x80x83EQ. 2
where D is a delay of one sampling period, D2 is a delay of two sampling periods, D3 is a delay of three sampling periods, and D4 is a delay of four sampling periods. Thus, in an EPR4 channel, the current channel output sample is the sum of a current input bit and the previous input bit, minus the second and third previous input bits. In an E2PR4 channel, the current channel output sample is the sum of a current input bit and two times the previous input bit minus two times the third previous input bit and minus the fourth previous input bit.
Because the EPR4 channel response involves the past three channel bits D, D2, and D3, there are eight possible states at each time period in the detector. Thus, an EPR4 channel requires an eight-state viterbi detector, which exist at the present time.
Because the eight-state Viterbi detector exists, most existing storage devices have an EPR4 target channel response. However, it has been shown that such channels suffer from single-bit error events defined as a single bit difference between the sequence of bits provided to the transmission channel and the sequence of bits estimated by the EPR4 detector.
One theoretical solution for removing these single-bit error events is to change the channel response to an E2PR4 response. Theoretically, this should remove the single-bit error because this error event generates a squared distance of 10, d2=10, in an E2PR4 channel compared to a squared distance of 4, d2=4, in the EPR4 channel. Such an increase in the squared distance generally makes it easier to detect the error in an E2PR4 channel than in an EPR4 channel.
Although this may work in theory, it is extremely difficult to implement because an E2PR4 detector is a sixteen-state machine that is significantly more complex than the eight-state machine of the EPR4 detector. In addition, the equalization strategy, timing and gain recovery associated with an E2PR4 channel is much more complex than the corresponding processes in an EPR4 channel. Thus, a detection system is needed that avoids the single-bit error of the EPR4 channel without adding the complexity of an E2PR4 channel.
A method for identifying errors in a detected sequence of values generates the detected sequence of values from channel samples using a detector designed for a channel with a first channel response characteristic. The detected sequence of values is filtered using a filter that emulates a second channel response characteristic to produce a sequence of simulated second channel samples. The channel samples provided to the detector are also provided to a second filter which emulates a response characteristic equal to the second channel response characteristic divided by the first channel response characteristic. This produces a sequence of actual second channel samples. A sequence of difference values is then generated by subtracting each of the simulated second channel samples from a corresponding actual second channel sample. Using the sequence of difference values, at least one error is identified in the detected sequence of values.
An apparatus under the present invention provides a detector capable of detecting a preliminary sequence of values from samples taken from a first channel""s output. A second channel filter is coupled to the detector and is capable of generating a sequence of simulated second channel samples from the preliminary sequence of values. A sequence of actual second channel samples is created from the samples at the first channel""s output by an equalizer filter that has a partial response characteristic such that the combined partial response characteristic of the first channel and the equalizer filter is equal to the partial response characteristic of the second channel filter. A difference circuit receives both the actual and simulated second channel values and produces a sequence of difference values by subtracting each simulated second channel value from a corresponding actual second channel value. A verification circuit then identifies errors in the preliminary sequence of values based on the sequence of difference values.